1. Field of the Invention
The present invention relates to the field of testing electronic devices. More specifically, the present invention relates to an improvement for efficiently testing programmable logic devices for manufacturing errors.
2. Related Art
Programmable logic devices (PLDs) provide programmable resources that can be configured to implement custom designs within an integrated circuit device or integrated circuit xe2x80x9cchip.xe2x80x9d The PLD can be a programmable logic device, such as a complex programmable logic device (CPLD), or a field programmable logic array (FPGA). These programmable logic devices contain generic functional modules that can be electrically coupled together and programmed to perform certain functions and generate specific signals such that a custom integrated circuit or PLD design can be realized in hardware. The programmable devices may also contain embedded memory blocks. Each memory block typically contains a number of outputs typically called data outputs. The integrated circuit device also contains a number of externally available input/output pins (I/O pins). The programmable resources within the PLD allow a memory, e.g., data, output to be selectively connected to an externally available I/O pin.
Integrated circuit devices that contain embedded memory blocks, such as PLDs, need to be tested after they are fabricated. The testing is done to detect any possible manufacturing faults or defects within the integrated circuit that would cause the device to operate in an unpredictable manner or in any manner that is not in accordance with the IC design. Typically, tester systems are attached to the device under test (DUT) and they stimulate the device with certain test patterns which are called logic vectors. The actual outputs of the DUT are then captured by the tester system and compared against a predetermined expected result (typically produced by device simulation). If the expected results and the actual outputs are different, then a fault or defect may be detected (and the device is rejected).
There are two possible methods for testing the embedded memory blocks of a programmable device. The first method allows the memory blocks to be tested in parallel by programming all outputs from every memory block to connect with the outputs of the chip, e.g., the externally available I/O pins. In the exemplary case of a 39K100 device, there are 24 embedded memory blocks, each with 8 outputs. Therefore, using this method of testing, a total of 192 I/O pins (external outputs) are required. One disadvantage of this testing method is that it requires a large number of I/O pins. This places a limitation on how many memory blocks can be tested in parallel due to the number of I/O pins available in a device package and it also places limitations on the test equipment and hardware. Not all testers have the capacity to test devices with this many I/O pins. Further, not all PLDs have this many I/O pins. What is needed is a testing method that does not require so many I/O pins.
The second method of testing embedded memory blocks of a programmable device allows a reduced set of I/O pins by testing each of the memory blocks one at a time and connecting only the memory block under test to the I/O pins of the chip. In the case of the 39K100 device, only 8 I/O pins are required but 24 separate tests are needed (one for each embedded memory block), and each test is done in series. A disadvantage of the second testing method is that it requires the memory blocks to be tested separately instead of in parallel. Therefore, the net test time increases dramatically. What is needed is a time efficient testing method that does not require so many I/O pins.
Accordingly, what is needed is a system and method for testing integrated circuits that is time efficient and that is efficient in the utilization of I/O pins. What is needed is a system and method for testing embedded memory blocks of a programmable device, e.g., a PLD, that is time efficient and that is efficient in the utilization of I/O pins. These and other advantages of the present invention not specifically recited above will become clear within discussions of the present invention presented herein.
A method and system are described for efficiently testing circuitry. A purpose of the present invention is to use logic available in a programmable logic device (PLD) to simplify testing of embedded memory blocks. This allows both the functionality and speed of all memory blocks to be tested simultaneously with a reduced set of output pins, e.g., two, rather than requiring direct testing of all outputs from every memory block.
The method and system may be applied to testing embedded memory circuit blocks within a PLD. Circuitry used in the testing process can be implemented from the programmable logic resources of the PLD, or alternatively, could be provided as specialized, dedicated test mode circuitry. The PLD may contain an arbitrary number, n, of memory blocks with each block having an arbitrary number, x, of output pins. An AND-tree circuit is implemented that receives each of the n*x output pins. If any pin is low, the output of the AND-tree is low, otherwise, the output is high. The output of the AND-tree is an input/output pin of the PLD. An OR-tree circuit is implemented that receives each of the n*x output pins. If any pin is high, the output of the OR-tree is high, otherwise, the output is low. The output of the OR-tree is another input/output pin of the PLD. The OR-tree and AND-tree circuits can be used to detect any manufacturing faults within the PLD and can also be used to measure the max/min delay timing of the memory block signals. During testing, predetermined patterns of logic are loaded into the memory blocks and read back in predetermined sequences using the AND-tree and OR-tree results. Using this method and system, a tester can be used that has reduced pin count and parallel testing can be performed.
More specifically, an embodiment of the present invention includes a programmable logic device comprising: a plurality of electronic circuits comprising a set of outputs and capable of receiving a test vector for parallel testing operations; an AND-tree circuit coupled to the set of outputs and for generating a first resulting output signal in response to the set of outputs; an OR-tree circuit coupled to the set of outputs and for generating a second resulting output signal in response to the set of outputs; and wherein the first and second output signals are for use by a tester system in detecting a defect within the plurality of electronic circuits by comparing the first and second resulting output signals to pre-defined first and second expected output signals. Embodiments also include the above and wherein the plurality of electronic circuits are a plurality of embedded memory blocks within the programmable logic device.
Embodiments include the above and wherein the AND-tree is implemented using configurable logic resources of the programmable logic device and wherein the OR-tree is implemented using configurable logic resources of the programmable logic device.
Embodiments include the above and wherein the first and second resulting output signals are for use by the tester system in determining a maximum signal delay time of the plurality of electronic circuits and wherein the first and second resulting output signals are for use by the tester system in determining a minimum signal delay time of the plurality of electronic circuits. Embodiments also include methods implemented in accordance with the above.